Flash memory is a non-volatile type of memory which can be rewritten and retain its data content without power. Flash and other types of electronic memory devices are constructed of memory cells that individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes having eight cells and words having sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells, where the data can then be retrieved in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is set to a known state. In typical single-bit flash devices, each cell has one of two possible data states, either a programmed state or an erased state, where the data states correspond to the two possible binary states of the corresponding bit (e.g., programmed state represents binary “0” and erased state represents binary “1”). More recently, cells structures have been developed that are capable of storing two physically separated bits, and other multi-bit structures have been proposed, in which different multi-bit data combinations are represented as electrically distinguishable programming levels in a given cell.
Conventional flash memory cells include a metal oxide semiconductor (MOS) device with a gate structure in which data may be retained in the form of trapped electrical charge. The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In a program or erase operation, the voltages are applied so as to cause a charge to be stored in the memory cell or removed from the cell, thereby changing or setting a threshold voltage of the cell. In a read operation, appropriate voltages are applied to cause a cell current to flow, wherein the amount of such current is related to the threshold voltage state of the cell and is thus indicative of the value of the data stored in the cell.
Conventional single-bit flash memory cells are often formed as a “stacked gate” or “SONOS” cell types. Stacked gate cells include a transistor structure having a source, a drain, and a channel in a substrate or p-well thereof, as well as a stacked gate structure overlying the channel that includes a gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. A doped polysilicon control gate overlies the interpoly dielectric layer to complete the stacked gate structure. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
Stacked gate cells can be programmed in a variety of ways. One common approach involves applying a relatively high positive voltage to the control gate while the source is grounded and the drain is connected to a predetermined positive potential above ground. This creates vertical and lateral electric fields along the length of the channel from the source to the drain, causing electrons to flow from the source and to begin accelerating toward the drain. As electrons move along the length of the channel, they gain energy to the point where some electrons are able to jump over the potential barrier of the tunnel oxide into the floating gate and become trapped in the floating gate (e.g., sometimes referred to as channel hot electron (CHE) injection). As a result of the trapped charge in the gate structure, the threshold voltage of the cell increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed (e.g., data “0”). Stacked gate cells may alternatively be programmed through Fowler-Nordheim tunneling of electrons from the substrate through the tunnel oxide by applying a positive control gate voltage while the substrate or body is held at ground or at a negative voltage, wherein electrons tunnel from the channel through the tunnel oxide and into the floating gate.
A stacked gate flash memory cell can be erased in a number of ways. In one arrangement, a relatively high positive voltage is applied to the source and the control gate is grounded while the drain is allowed to float. A strong electric field is developed across the tunnel oxide between the floating gate and the source, causing electrons that were trapped in the floating gate to undergo Fowler-Nordheim tunneling through the tunnel oxide into the source. In another arrangement, a negative voltage is applied to the control gate, and a positive voltage is applied to the source while the drain is allowed to float. Alternatively, a positive voltage is applied to the substrate and a negative voltage is applied to the control gate while the source and drain are floated to erase the cell through Fowler-Nordheim tunneling of electrons from the floating gate into the substrate.
Conventional SONOS type cells (e.g., silicon-oxide-nitride-oxide-silicon) also include an ONO structure formed over the substrate channel, with a control gate formed over the ONO structure, but without a floating gate. To program the SONOS cell, electrons are transferred from the substrate to the nitride layer in the ONO structure by applying appropriate voltage potentials to the cell terminals. Because the nitride is generally non-conductive, the trapped electrons tend to remain localized, whereby two spatially separate bits may be stored in a single cell, for example, by applying positive gate and drain voltages while the substrate is grounded, thereby creating vertical and lateral channel fields. This causes electrons to be trapped in the ONO structure near the drain end of the cell. Reversing the source and drain voltages can cause charge trapping (e.g., programming) to occur near the source end. Alternatively, SONOS cells can be programmed by Fowler-Nordheim tunneling of electrons from the substrate into the ONO structure by applying a positive gate voltage and grounding the substrate. As with stacked gate cells, SONOS type flash cells are erased by causing the trapped electrons to migrate from the ONO structure back into the substrate through application of suitable voltages to the substrate, gate, source, and/or drain. For example, SONOS cells may be erased by grounding the substrate, source, and drain, and applying a negative gate voltage, causing Fowler-Nordheim tunneling of electrons from the ONO structure into the substrate.
A continuing trend in flash and other types of memory device designs is the reduction of device dimensions, referred to as scaling. As a result, it is desirable to reduce the size of various structures that make up flash memory cells. Another design goal is to reduce the power consumption and operating voltages in flash memories. In addition, it is desirable to increase the number of program/erase operations of flash memory devices and to shorten the time required to perform read, program, and erase operations. Furthermore, it is desirable to construct flash memory cells with improved data retention capabilities. Accordingly, there remains a need for improved flash memory devices as well as fabrication and operational methods by which these design goals can be facilitated.